This invention relates to a package structure for a semiconductor device in which a semiconductor chip is wirebonded by the tape carrier bonding method.
The tape carrier bonding method (TAB method) is one of the wireless bonding methods. Since the TAB method allows high speed automatic bonding, the number of the semiconductor devices manufactured by this method is increasing.
When a semiconductor chip to which a bottom surface electrical potential is to be applied is manufactured by the TAB method, the bottom surface contact is obtained by bonding the bottom surface of the semiconductor chip to wiring on the substrate. The wiring is connected to a terminal electrode on the upper surface of the semiconductor chip by means of a lead conductor.
FIG. 1 is a perspective view showing a semiconductor chip secured on a tape base material by the TAB method, and FIG. 2 is a sectional side view of the semiconductor chip mounted to a substrate. In these FIGS. a semiconductor chip 1 has projecting electrodes 2 formed on its top surface. A tape base material 3 has formed therein an opening 3a within which the semiconductor chip 1 is disposed, and outer lead slits 3b along which the semiconductor chip is separated from the tape base material 3 during the semiconductor chip separating process which will be described in detail later. A plurality of lead wires 4 each including an inner lead 4a, an outer lead 4b and a test pad 4c are bonded to the tape base material 3. Thus, the semiconductor chip 1 is secured to the tape base material 3 by hot press bonding the projecting electrodes 2 of the semiconductor chip 1 to the inner leads 4a by the inner lead bonding step in the TAB method. The projecting electrodes 2 may be formed on the inner leads 4a instead of being formed on the semiconductor chip 1.
As seen from FIG. 2, the semiconductor chip 1 and the tape base material 3 are secured and protected by a sealing resin material 5. In order to electrically connect the semiconductor device and an external circuit, a substrate 6 is provided. The substrate 6 has formed on its upper surface substrate wiring 7a to which the outer lead 4b is connected, and substrate wiring 7b to which the bottom surface of the semiconductor chip 1 is electrically bonded by an electrically conductive bonding agent 8. The assembly formed on the substrate 6 is coated by a package resin 9.
During manufacture, the semiconductor chip 1 mounted to the tape base material 3, together with the outer leads 4b, is punched from the tape base material 3 at the position corresponding to the outer lead slits 3b with predetermined dimensions. Then, the free ends of the outer leads 4b are bonded to the substrate wiring 7a and the bottom surface of the semiconductor chip 1 is bonded to the substrate wiring 7b. The bottom surface of the semiconductor chip 1 must also be electrically connected to the selected one of the projecting electrodes 2 on the top surface of the semiconductor chip 1 by means of the substrate wiring 7b and an unillustrated lead wire between the substrate wiring 7b and the electrode 2.
Thus, the semiconductor chip requiring a bottom surface potential and mounted to the tape base material by the TAB method has an electrical connection between its top and bottom surfaces only after the semiconductor chip has been finally bonded to the surface. Therefore, it is impossible to conduct the necessary test on the semiconductor device immediately after the bonding of the inner leads. For these reasons, it was impossible to "burn in" the semiconductor devices in which the inner leads are not properly bonded to the semiconductor chip or the semiconductor devices in which a defect is generated within the semiconductor chip during the application of the sealing resin, decreasing the yield of the product. Also, the substrate to which the defective semiconductor chip has been bonded must be discarded even if the substrate itself is satisfactory.